1. Field of the Invention
This invention relates to computer systems. In particular, the invention relates to processing serial data using a single receive first-in first-out (FIFO) buffer.
2. Description of Related Art
The Institute of Electrical and Electronics Engineers (IEEE) 1394 is a high-speed serial interconnect that makes the convergence of consumer electronics and personal computers (PCs) possible. Products supporting 1394 protocols at 100 to 400 Megabits/sec (Mbps) are now commercially available. Products with speeds up to 3200 Mbps are available in a near future.
To promote product development and enhance industry, the Open Host Controller Interface (OHCI) specification defines basic protocols and operational modes to support the IEEE 1394 standard and its enhancements (e.g., 1394a).
An OHCI-compliant device has both transmitter and receiver functionalities and acts as an interface between the host processor in the PC and the physical link to the 1394 peripheral devices. To enhance transfer rate, direct memory access (DMA) engines are used to transfer data in and out of the host processor""s memory. In addition, first-in-first-out (FIFO) memories are used to buffer transmitted and received data for the corresponding DMA engines.
There are a number of problems associated with the FIFO-based receive and transmit contexts. On the receive side, these problems include context shutdown, context decoding, and packet trailer processing. On the transmit side, one problem is the proper flushing of an asynchronous transmit packet after a bus reset.
A context shutdown refers to a process in which a DMA engine is shut down and does not process packet data further. One way to implement a context shutdown mechanism is to provide external logic to keep track of the number of packets for each context that are in the FIFO at any given time. This method, however, requires additional hardware and adds complexity to the device. Another way is to merely flush the received packet data in the FIFO after shutting down and provide the status information to the host software. This method wastes data bandwidth because the received packet data are discarded unnecessarily.
Context decoding refers to a process in which the received packet is decoded prior to being transferred to the appropriate DMA engine for further processing. The packet information useful for DMA processing includes packet type, length, speed code, errors, etc. One method for context encoding/decoding is to include the packet information for DMA processing in the packet header. This method, however, requires the DMA engine to examine the packet header, incurring processing time. Another method is to provide external logic to keep track of the start and end points within a FIFO. This method, however, is expensive and places arbitrary limits on the number of packets that could be contained within the FIFO.
Packet trailer processing refers to the process in which a 32-bit packet trailer is written into memory as required by the 1394 OHCI. One way to do this is to write the packet trailer as a stand-alone operation after the packet has been written into the memory. This method, however, wastes bandwidth due to additional overhead for the DMA engine to process the packet trailer separately.
Flushing an asynchronous transmit (AT) packet refers to a process of discarding the AT packet in the FIFO after a 1394 bus reset. A bus reset may change the destination identification (ID) code for the packet. Therefore, after a bus reset, the packet data in the FIFO may still contain the old destination ID which is no longer valid. One way to flush the invalid packets is to read each entry in the FIFO to flush the entire FIFO. However, for a 256-entry FIFO, this flushing may take up to 256 clocks. This can be a long wait when there are many DMA transmit packets ready to be sent to the AT FIFO
Therefore there is a need in the technology to provide an efficient technique to process the serial packet data for receive FIFO and flushing of transmit FIFO data after a bus reset.
The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.